Digital Oscilloscope Design Files

The Alpha revision boardThe other day I said that the original oscilloscope hardware has been retired and a new version is in the design process. Below I have documented all the parts of the original hardware and have attached the schematics, board files and code.

High Speed USB2 interface board

Cypress FX2 (CY7C68013A-128AXC)

The chip is very easy to wire up, only requiring a 24MHz crystal, some EEPROM and reset switch. A few decoupling caps are needed, nothing substantial, but you will need to generate a 3V3 rail to power the core of the enhanced 8051 processor. This was generated with a small LT1763 fixed output regulator able to supply 500mA – more than enough to run the chip.

There are 2 40pin headers on the bottom of the board the supply 2.54mm connections to all of the chips IOs. This allowed the FPGA to use the GPIF bus to transfer data at up to 96Mbytes/s.

FPGA and ADC ‘data crunching’ board

Xilinx FPGA (XC3S50ATQ144)

The FPGA can be wired up in whatever way you want – within certain limits though. As this was the first time we had ever used FPGAs, we went for which pins were the easiest to wire up, not necessarily the best choice for noise and other considerations. A simple SMD oscillator was used as a master clock input. 16 decoupling caps were used for the FPGA but the power supplies were still pretty unstable – more about that later.

Maxim ADC (MAX1198)

This dual 8-bit 100MSPS ADC is the core of the oscilloscope. It takes the conditioned signal from the input boards, buffers it (using a LMH6555) and centres it on a reference voltage to be sampled by the ADC. The data then goes on to the FPGA which will pipe it upstream to the computer over USB. Several decoupling caps are also used for the ADC to try to keep noise to a minimum.

SDRAM (MT46V16M16)

The module (see right) is fairly easy to implement by simply connecting pretty much all of the pins to the FPGA for it to control. Unfortunately though due to the FPGA not having a dedicated memory controller, some hardware oversights and not enough space on the FPGA, this module was never implemented or tested.

FX2 Header

The FX2 is being used to program the FPGA over JTAG, and also provides a 16bit wide data bus to transfer the data over USB from the FPGA.

Power House

All linear regulators were used to power the FPGA board from a separate wall supply because USB couldn’t supply enough current. They were all fixed regulators so no feedback resistors are needed and we followed the standard manufacturer recommendations for input and output caps. Unfortunately when the scope was in use, we have a huge amount of noise on the power rails making the scope trace almost un-recognisable. Some reference voltages were created from a simple buffered voltage divider – probably not the best way in hindsight.

Single ended input board

This input board converts a single ended input (that can be AC or DC coupled) into a differential signal using an Instrumentation Amplifier. A PIC is used to control the AC coupling capacitor (using a relay) which communicates with the FPGA over serial. This feature was never fully implemented either.

Differential input board

This board uses a multiplexer to select different resistor values in an op-amp circuit to change the accepted input voltage range. The on-board PIC controls the AC coupling again and also controls the multiplexer to control the attenuation.

Why was this board retired?

The board was retired mainly due to several major hardware oversights but the project was always going to be an experiment as we had never used FPGAs before. The power supplies are incredible noisy causing major distortion on the input signals (see left) which is never good! The FPGA was also not large enough to contain all of the required code to get everything running. The DDR module was never implemented because none of the traces are the same length and we did not include a vital ‘timing loop’ for the FPGA to adjust timings appropriately. The input boards also seem to not be working terribly well. The input signals mainly disappear from existence – not ideal for an oscilloscope!

Due to all of these problems, V1.0 boards were retired and now the ‘beta-scope’ boards are being designed. We will also need some funding from places like KickStarter, but unfortunately UK residents cannot use KickStarter – such a shame.

Design Files

The project was always designed to be open source, so here are all of the source files:

Scope v1.0 Eagle Design Files

GitHub Firmware Repository


Wednesday, May 2nd, 2012 Electronics Projects

5 Comments to Digital Oscilloscope Design Files

  • Ruben M. says:


    I am very interested in this project and have laid out some ideas based on this concept. I’ve thought of it for quite some time, but never got my hands busy with it.

    I would like to help in any way I could. I’m eligible to start a Kickstarter. I think that could be a start!

    Let me know if you are interested.


  • Fred says:

    Hi Ruben
    Thanks for your interest. If you have any files online, or even any ideas, I would love to have a look. It is always interesting to see how other people go abut a similar project.
    I don’t think we can use someone in the US to use KS for us – I’m sure that breaks some rules somewhere! Thanks for the offer though. I might have a look at in the UK – but it doesn’t look anywhere as big as KS unfortunately.

  • Hi Atom
    Is this scope to be used with a PC so where can I faind the software interface.
    Best regrds

  • Fred says:

    Hi Nelson
    The computer software was never written as the hardware is being revised. The bitstream used to be pulled raw from the ADC to the computer through the FPGA which we then reconstructed into a waveform.

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